Featured Projects

Budget Flow
Budget tracking web app built at TartanHacks (CMU)
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Simple 8-Bit CPU
CPE-271 (Digital Logic) final project using VHDL to design a CPU
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CMOS Inverter & Logic Circuit Design
Designed, simulated, and optimized noise margins for a CMOS inverter and a clocked CMOS circuit
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Contact Me
Email: brianngo2948@gmail.com
LinkedIn: Brianngo9
Instagram: Brian_Ngo9
